The present invention relates generally to processing systems which include one or more devices that interface with a host processor, and more particularly to techniques for transferring data between the host processor and a device of the system.
There are many processing system applications in which a processing device of the system interfaces with a host processor. For example, the processing device may be an application-specific integrated circuit (ASIC) designed to perform a given data processing function, and the host processor may be utilized to store and supply data relating to the processing function, to perform computations associated with the processing function, or to program the ASIC with the specific operating parameters required in a given implementation.
A more particular example of a processing device of the type described above is commonly referred to as a network processor. A network processor generally controls the flow of packets between a physical transmission medium, such as a physical layer portion of, e.g., an asynchronous transfer mode (ATM) network or synchronous optical network (SONET), and a switch fabric in a router or other type of packet switch. Such routers and switches generally include multiple network processors, e.g., arranged in the form of an array of line or port cards with one or more of the processors associated with each of the cards. In this type of arrangement, each of the line or port cards will generally include a host processor, and the host processor of a given line or port card can be utilized to direct the storage of data in and retrieval of data from a host memory, to perform computations on behalf of the network processor, and to configure the network processor for particular operating parameters.
A host processor typically communicates with an associated network processor or other processing device through the use of a standard communication bus architecture, such as the well-known Peripheral Component Interconnect (PCI) bus described in, e.g., PCI Local Bus Specification, Rev. 2.2, which is incorporated by reference herein.
There are a number of significant problems with conventional communication bus architectures such as the above-noted PCI bus. For example, the utilization of the available bus bandwidth tends to be inefficient in many applications. In addition, excessively large memory allocations are often require to implement the above-noted transfer of packets or other data to and from the host memory. Another problem in the packet transfer context is that previous techniques typically require a certain byte alignment, which may unduly limit the byte size of the packets that may be transferred.
It is therefore apparent that a need exists for improved techniques for implementing data transfers between a host processor and a network processor or other processing device in a manner which alleviates one or more of the above-noted problems.
The invention provides improved techniques for transferring data between a host processor and a processing device in a data processing system.
In accordance with one aspect of the invention, the processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor controls the transfer of information to or from scattered or non-contiguous memory locations in a memory associated with the processing device, utilizing a data structure comprising a single descriptor. The information to be transferred is characterized by address and data information stored in a specified region of a host memory associated with the host processor. The non-contiguous memory locations associated with the processing device may be non-contiguous memory locations in a target block memory or a set of configuration registers in an internal memory of the processing device. The single descriptor scatter gather technique allows an information transfer bandwidth of the system bus to be more efficiently utilized than if a separate descriptor were used for transfer of information involving each of the non-contiguous memory locations.
In accordance with another aspect of the invention, the scatter gather data transfer is implemented using a descriptor table stored in a memory of the host processor and defined by a descriptor head pointer and a descriptor tail pointer. The descriptor table may include multiple descriptor entries, each of the entries defining a particular region of the host memory associated with a corresponding descriptor. The particular region of the host memory associated with the corresponding descriptor is utilized in implementing a data transfer between the host processor and the processing device in accordance with that descriptor. The descriptor table is generated under the control of one or more software programs executable by the host processor.
The processing device may be a network processor configured to provide an interface between a network and a switch fabric in a router or switch.
Advantageously, a scatter gather data transfer in accordance with the invention is implemented using only a single descriptor, which reduces congestion on the system bus, thereby improving the efficiency of the bus bandwidth utilization, while also overcoming one or more of the other problems associated with conventional data transfer techniques.